Logic system for sequentially testing the states of a system of contacts

ABSTRACT

A logic system for sequentially testing the states of a system of contacts: It is characterized in that it comprises: 2n p contacts to be tested, n and p being integers greater than 1, the contacts being tested by groups of 2m contacts, m being an integer less than n; a diode matrix comprising 2n columns and 2p rows wherein each diode is in series with one of the contacts to be tested, each column is embodied by a bus bar having one end connected via a load resistance to one pole of a battery whose other pole is earthed, and each row is earthed via a switching transistor called a &#39;&#39;&#39;&#39;row transistor&#39;&#39;&#39;&#39;; 2m contact position reading circuits each comprising a diode logic or-circuit having 2n m inputs, each of the 2n bus bars being connected to just one of the latter inputs, the output of each logic or-circuit being connected via two diodes in series to the base of a transistor called &#39;&#39;&#39;&#39;reading transistor&#39;&#39;&#39;&#39; whose emitter is earthed and whose collector is connected to an amplifier for detecting whether the reading transistor is in the conductive or non-conductive state, each such state corresponding to one of the positions of the tested contact; and an address counter having 2n p m addresses which are decoded through the agency of the matrix and of a selector circuit comprising diode logic or-circuits having their outputs earthed via a switching transistor called &#39;&#39;&#39;&#39;selecting transistor&#39;&#39;&#39;&#39; and their inputs connected to the bus bars, so that during the decoding of an address the selecting circuit earths every input but one of each reading circuit and only one of the row transistors is in the conductive state.

United States. Patent [191 Nahon m1 3,872,324 1 Mar. 18, 1975 LOGICSYSTEM FOR SEQUENTIALLY TESTING THE STATES OF A SYSTEM OF CONTACTS [75]Inventor: Poland Nahon, Paris, France [73] Assignee:,leumont-Schneiden-Paris(Seine),

France 221 Filed: June 14, 1974 21 Appl. No.: 479,475

Related US. Application Data [63] Continuation of Ser. No. 300,328, Oct.24, 1972,

abandoned.

[30] Foreign Application Priority Data Oct. 21, 1971 France 71.37793[52] US. Cl 307/241, 307/218, 307/253, 317/137, 324/28 R, 340/166 R,179/18 [51] Int. Cl H03k l7/00, GOlr 31/02 [58] Field of Search 307/203,218, 239, 241,

[56] References Cited UNITED STATES PATENTS 2,902,642 9/1959 Vocgtlen324/28 R 7 2,997,646 8/1961 Voegtlen 324/28 R 3,253,214 5/1966 Heilweilet 111.... 324/28 R 3,363,064 1/1968 Spcrlich 179/18 PrimaryExaminer-Stanley D. Miller, Jr. I Attorney, Agent, or FirmRayniond A.Robic; Arthur Schwartz; David A. Blumenthal V 7 [57 ABSTRACT A logicsystem for sequentially testing the states of a system of contacts: Itis characterized in that it comprises: 2" contacts to be tested, n and pbeing integers greater than 1, the contacts being tested by groups of2'" contacts, 771 being an integer less than n; a diode matrixcomprising 2" columns and 2" rows wherein each diode is in series withone oi the contacts to be tested, each column is embodied by a bus barhaving one end connected via a load resistance to one pole of a batterywhose other pole is earthed, and each row is earthed via a switchingtransistor called a row transistor; 2" contact position reading circuitseach comprising a diode logic orcircuit having 2"'"' inputs, each of the2 bus bars being connected to just one of the latter inputs, the outputof each logic or-circuit being connected via two-diodes in series to thebase of a transistor called reading transistor whose emitter is earthedand whose collector is connected to an amplifier for detecting whetherthe reading transistor is in the conductive or non-conductive state,each such state corresponding to one of the positions of the testedcontact; and an address counter having 2"*""" addresses which 7 aredecoded through the agency of the matrix and of a selector circuitcomprising diode logic or-circuits having their outputs earthed via aswitching transistor called selecting transistor" and their inputsconnected to the bus'bars, so that during the decoding of an addresstheselecting circuit earths every input but one of each reading circuitand only one of the row transistors is in the conductive state.

- lrClaim 1 Drawing Figure ii] i i iiii 5i" Vi, a? a, a

LOGIC SYSTEM FOR SEQUENTIALLY TESTING THE STATES OF A SYSTEM OF CONTACTSThis is a continuation, of application Ser. No. 300,328, filed Oct. 24,1972, now abandoned.

This invention relates to a logic system for sequentially testing thestates or positions of a system of contacts, e.g. relay contacts.

Testing systems of this kind are known, but most of the known systemshave the disadvantage of not being able to provide simultaneous testingof the position of more than one contact, unless a great number ofcomponents is used.

This invention obviates this disadvantage and enables a number ofcontacts to be thus tested at relatively low cost.

The system according to the invention is characterized in that itcomprises:

2" contacts to be tested, n and p being integers greater than I, thecontacts being tested by groups of 2" contacts, m being an integer lessthan n;

a diode matrix comprising 2" columns and 2' rows wherein each diode isin series with one of the contacts to be tested, each column is embodiedby a bus bar having one end connected via a load resistance to one poleof a battery whose other pole is grounded, and each row is grounded viaa switching transistor called a row transistor;

2'" contact position reading circuits each comprising a diode logicor-circuit having 2""" inputs, each of the 2" bus bars being connectedto just one of the latter inputs, the output of each or-elernent beingconnected via two diodes in series to the base of a transistor calledreading transistor whose emitter is earthed and whose collector isconnected to an amplifier for detecting whether the reading transistoris in the conductive or non-conductive state, each such statecorresponding to one of the positions of the tested contact, and

an address counter having 2""' addresses which are decoded through theagency of the matrix and ofa selector circuit comprising diode logicor-circuits having their outputs earthed via a switching transistorcalled selecting transistor and their inputs connected to the bus bars,so that during the decoding of an address the selecting circuit earthsevery input but one of each reading circuit and only one of the rowtransistors is in the conductive state.

The invention will be more clearly understood with the help of anembodiment and of the single accompanying, representing the circuitdiagram of a logic system for testing the states i.e., whether they areclosed or open of a group of 256 relay contacts numbered from 1 to 256and grouped in 16 groups having the Roman numeral references I to XVI,each group comprising sixteen each contact in series with one diode. Allthat the single FIGURE shows is the first group I and the last group XVIeach surrounded by chaindotted line framing, so as not to make thediagram unnessarily complicated.

In the example chosen, n 4, p 4. The diode matrix, in which each diodeis in series via its cathode with one of the contacts whose open orclosed state it is required to determine, comprises 16 rows and 16columns. Each row is connected to the collector of an NPN transistorcalled a row transistor t (whose index represents the row rank), thetransistor emitter being grounded. The 16 row transistors act asswitches, according to the kind of signal applied to their base.

The 16 matrix columns are embodied by 16 bus bars (not shown in ordernot to overload the diagram) but indicated by the letters aA bB cC dD eEfF gG hH. The bus bars have one end connected to the matrix diode anodesand the other end connected to the positive pole of a DC supply S via aload resistance R.

The contacts are tested in groups of two, m being equal to unity. Thereare two reading circuits each comprising a diode logic or-circuit whoseinputs (which are the diode anodes) are respectively connected to thebus bars having lower-case references in the case of the first logicor-circuit and to the bus bars having uppercase references in the caseof the second logic orcircuit. By way of two diodes D in series, theoutput of each or-element is connected to the base of an NPN transistorT or T called reading transistor whose emitter is grounded and whosecollector is connected to an amplifier L or L called reading amplifier.

The selecting circuit comprises the six logic orcircuits at the bottomof the drawing. The first two have eight inputs connected to the busbars aA bB cC dD and to the bus bars eE fF gG hH. The last four havetheir inputs connected to bus bars aA eE, bB fF, cC gG, dD hHrespectively. The outputs of these six orelements are connected to thecollector of an NPN transistor V V V V V V respectively-whose emitter isgrounded.

A resistance R, is connected between the base and the emitter of all thetransistors t, T and V.

An address counter having 128 addresses is used to test the state ofeach of the 256 contacts.

The encoding of the addresses is so devised in known manner that foreach address the bases of the following transistors are renderedconductive through connection of the transistors to ground:

a single one of the row transistors 1 to one of the transistors V or Vand i all the transistors V V V ,V ,ex cept one.

Consequently, the entire system shown in the drawing acts as a decodingselector of the 128 addresses. Assuming that the following transistorshave been made conductive: 1

t alone of the 16 row transistors;

V but not V V V V but not V since transistor V is conductive, bars aA bBcC dD are grounded.

Since transistor V is conductive, bars bB fF are grounded.

Since transistor V is conductive, bars cC gG are grounded.

Since transistor V is conductive, bars dD hl-I are grounded.

Consequently, only bars e and E are not grounded, and a current can flowthrough them and through the transistor t Consequently, the onlycontacts whose position can be tested are the contacts 9, 10.

If contact 9 is closed, since bar e is grounded via transistor tamplifier L has no voltage applied to it since the two seriallyconnected diodes D cut off the transistor T lf contact 9 is open, bar eis not grounded through transistor t but a current flows through the twodiodes D connected to the base of transistor T Since the same isconductive, a voltage is applied to reading amplifier L Consequently,the open or closed state of contact 9 can be ascertained by means ofamplifier L Also, since bar E is not earthed, transistor T is eitherconductive or cut off, for the same reasons as just given, according ascontact 10 is open or closed, and the state of contact 10 is indicatedby amplifier L Consequently, the state of just one definite pair ofcontacts can be tested by decoding each address. Stepping-on of theaddress counter changes over the bases of the transistors rand V andenables the other pairs of contacts to be read. The state of thecontacts can be cyclically tested either periodically or continuously.

If the number of contacts to be dealt with is other than a power of two,the diode matrix must have a number of intersections equal to the nextpower of two above the number of contacts, and the number of extraintersections thus used can be considered, for instance, ascorresponding to complementary imaginary contacts which are always open.

The embodiment has been dealt with on a positive logic basis, with diodelogic circuits and with switching transistors. Transposing the testingsystem to a negative logic basis or the use of means equivalent totransistors and to the diode circuits falls under the invention.

I claim:

1. A logic circuit for testing the states of an array of contactscomprising:

a. 2'' contacts to be tested, 11 and p being integers greater than 1,the contacts being tested by groups of 2'", m being an integer less thann;

b. a diode matrix comprising 2" columns and 2" rows wherein each diodeis in series with one of the contacts to be tested, each column isconnected to one of a plurality of 2" bus bars, each bus bar having oneend connected via a load resistance to one pole of a battery whose otherpole is grounded, and each row is grounded via row switching means;

c. 2'" reading circuits each comprising a diode logic or-circuit having2""" inputs and a single output, each of the 2" bus bars being connectedto only one of said reading circuit inputs the output of each logicor-circuit being connected to the base of a reading transistor saidreading transistor connected to an amplifier for detecting whether thereading transistor is in the conductive or non-conductive state, eachsuch state corresponding to one of the positions of the tested contact;

d. an address counter having 2"*" addresses; and

e. decoding means connected to said address counter and comprisingselector circuits having diode logic or-circuit elements, said elementshaving outputs grounded via a selecting transistor and inputs connectedto said bus bars, said decoding means grounding every input but one ofeach of said reading circuits and said decoding means triggering onlyone of said row switching means into a conducting state.

1. A logic circuit for testing the states of an array of contactscomprising: a. 2n p contacts to be tested, n and p being integersgreater than 1, the contacts being tested by groups of 2m, m being aninteger less than n; b. a diode matrix comprising 2n columns and 2p rowswherein each diode is in series with one of the contacts to be tested,each column is connected to one of a plurality of 2n bus bars, each busbar having one end connected via a load resistance to one pole of abattery whose other pole is grounded, and each row is grounded via rowswitching means; c. 2m reading circuits each comprising a diode logicor-circuit having 2n m inputs and a single output, each of the 2n busbars being connected to only one of said reading circuit inputs theoutput of each logic or-circuit being connected to the base of a readingtransistor said reading transistor connected to an amplifier fordetecting whether the reading transistor is in the conductive ornon-conductive state, each such state corresponding to one of thepositions of the teSted contact; d. an address counter having 2n p maddresses; and e. decoding means connected to said address counter andcomprising selector circuits having diode logic or-circuit elements,said elements having outputs grounded via a selecting transistor andinputs connected to said bus bars, said decoding means grounding everyinput but one of each of said reading circuits and said decoding meanstriggering only one of said row switching means into a conducting state.